发明名称 PROCESSOR ARRANGEMENTS AND A METHOD FOR TRANSMITTING A DATA BIT SEQUENCE
摘要 A processor arrangement is provided. The processor arrangement includes: a first processor; a plurality of second processors, each second processor including a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor includes a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.
申请公布号 US2014189176(A1) 申请公布日期 2014.07.03
申请号 US201213729052 申请日期 2012.12.28
申请人 INFINEON TECHNOLOGIES AG 发明人 Klug Franz;Sonnekalb Steffen
分类号 G06F13/38 主分类号 G06F13/38
代理机构 代理人
主权项 1. A processor arrangement, comprising: a first processor; a plurality of second processors, each second processor comprising a bit-mask generator configured to generate a processor-specific bit-mask sequence; wherein the first processor comprises a bit-mask generator configured to generate the processor-specific bit-mask sequences of the second processors; wherein the first processor is configured to bit-mask a data bit sequence to be transmitted to one second processor of the plurality of second processors using a processor-specific bit-mask sequence specific to the one second processor, to thereby generate a processor-specific bit-masked data sequence to be transmitted to the one second processor.
地址 Neubiberg DE