TRANSITION DELAY DETECTOR FOR INTERCONNECT TEST

摘要

A test circuitry configured to test for transition delay defects in inter-die interconnects is disclosed. In one aspect, the test circuitry comprises an input port configured to receive a test data value and a data storage element configured to temporarily store the test data value. The test circuitry additionally comprises a second inter-die interconnect configured to be electrically connected to a first inter-die interconnect so as to form a feedback loop for transferring the test data value from the data storage element back to the data storage element. The test circuitry additionally comprises a data conditioner configured to condition the fed back test data value so as to make it distinguishable from the stored test data value. The test circuitry additionally comprises a clock pulse generator configured to generate a delayed clock pulse. The test circuitry additionally comprises a selection logic configured to apply the generated delayed clock pulse and the conditioned fed back test data value to the data storage element. The test circuitry further comprises a readout unit for reading out a test data value stored in the data storage element.