发明名称 Creating a standard cell circuit design from a programmable logic device circuit design
摘要 A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist, mapping logic gates of the netlist to functionally equivalent standard cells, and including the standard cells within the standard cell circuit design. Design constraints for the standard cell circuit design can be automatically generated. The design constraints for the standard cell circuit design can be output.
申请公布号 US8667437(B2) 申请公布日期 2014.03.04
申请号 US20080049676 申请日期 2008.03.17
申请人 RAJE SALIL RAVINDRA;GAITONDE DINESH D.;XILINX, INC. 发明人 RAJE SALIL RAVINDRA;GAITONDE DINESH D.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址