发明名称 Delay locked loop
摘要 A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the delay clock, a delay locked loop configured to perform a delay locking operation using a signal delivered from the selection unit, and a selection control unit configured to control the selection unit in response to a comparison of one period of the inputted clock and a maximum delay value of the delay locked loop.
申请公布号 US8638137(B2) 申请公布日期 2014.01.28
申请号 US201213448547 申请日期 2012.04.17
申请人 CHUNG JIN IL;HYNIX SEMICONDUCTOR INC. 发明人 CHUNG JIN IL
分类号 H03L7/06 主分类号 H03L7/06
代理机构 代理人
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