| 摘要 |
A computing device [600] for performing real-time and mixed criticality tasks has at least one sub-computing device [608, 609]. Each sub-computing device has at least one bus, [101, 601] at least one bus master [605, 606, 611, 612, 613, 614], at least one memory store, [222, 232]. At least one of the at least one sub-computing devices [608, 609] has at least two bus masters [605, 606, 611, 612, 613, 614], and a means [101, 601, 605, 606] to enable or disable at least one of the at least two bus masters [605, 606, 611, 612, 613, 614] from issuing memory transfer requests onto the bus [101, 601] without resetting the at least one of the at least two bus masters [605, 606, 611, 612, 613, 614]. In another aspect, the computing device [600] has at least two cache modules [223, 224, 233, 234] arranged in parallel. The first cache module [223, 224, 233, 234] has an input address space of at least 1 kilobyte in length. The computing device [600] has at least one bus master [611, 612, 613, 614]. A first bus master [611, 612, 613, 614] can perform memory transfer requests with both the first cache module [223, 224, 233, 234] and another cache module [223, 224, 233, 234]. The computing device [600] has at least one memory store [222, 232]. A first contiguous subset of the input address space of at least 1 kilobyte in length of a first memory store [222, 232] is bijectively mapped as cacheable with at least a contiguous subset of the input address space of the first cache module [223, 224, 233, 234], and bijectively mapped as cacheable with at least a subset of the output address space of the first bus master [611, 612, 613, 614]. In another aspect a computing device [1200] has N > 1 sub-computing devices [1220, 1240, 1260]. Each sub-computing device [1220, 1240, 1260] has at least one bus [1221, 1241, 1261], at least one bus master [1230, 1231, 1291, 1292, 1243, 1263, 1295, 1296] that is a processor [1230, 1231, 1243, 1263], and has the bus slave interface of at least one memory store [1293, 1294, 1281] connected to one of the busses [1221, 1241, 1261]. The computing device has at least one unidirectional bus bridge [1291, 1292, 1295, 1296] that is connected to one of the sub-computing devices [1220, 1240, 1260]. The computing device has at least one memory store [1293, 1294, 1281] that is connected to two of the sub-computing devices. Specifically, X of the N sub-computing devices 1220, 1240, 1260] are directly connected to a common bus [1221] by a corresponding bus bridge [1291, 1292, 1295, 1296] where the value of X is 2 <= X <= N. A first set of two of the sub-computing devices [1220, 1240, 1260] are connected to each other by a first memory store [1293, 1294, 1281]. |
