发明名称
摘要 Gain setting can be performed at high speed while reducing DC offset due to a filter cutoff frequency changeover without the need for input signal muting. A filter circuit having first and second filters is capable of allowing settings of first and second cutoff frequencies. First and second filter switch circuits and a charging circuit including a charging resistor and a charging switch are provided. For a first time period, the first switch circuit is controllably turned on while the second switch circuit is controllably turned off, thereby providing the first filter function. For a second time period, the first switch circuit is controllably turned off while the second switch circuit is controllably turned on, thereby providing the second filter function. For the first time period, the charging switch is controllably turned on so that the second capacitor is charged via the charging resistor.
申请公布号 JP5270488(B2) 申请公布日期 2013.08.21
申请号 JP20090180415 申请日期 2009.08.03
申请人 发明人
分类号 H04B1/30 主分类号 H04B1/30
代理机构 代理人
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