发明名称 |
Parallel pipelined calculation of two calibration values during the prior conversion cycle in a successive-approximation-register analog-to-digital converter (SAR-ADC) |
摘要 |
A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.
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申请公布号 |
US8421658(B1) |
申请公布日期 |
2013.04.16 |
申请号 |
US201113304346 |
申请日期 |
2011.11.24 |
申请人 |
YAU HOK MO;WU TIN HO (ANDY);WAN KAM CHUEN;WONG YAT TO (WILLIAM);HONG KONG APPLIED SCIENCE & TECHNOLOGY RESEARCH INSTITUTE COMPANY, LTD. |
发明人 |
YAU HOK MO;WU TIN HO (ANDY);WAN KAM CHUEN;WONG YAT TO (WILLIAM) |
分类号 |
H03M1/10 |
主分类号 |
H03M1/10 |
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