发明名称 Method of forming a via and method of fabricating chip stack package thereof
摘要 <p>PURPOSE: A method for forming a via and a method for manufacturing a stack chip package using the same are provided to supply a solution with metal particles to a via hole to process a substrate at a lower temperature, thereby quickly and simply forming a via. CONSTITUTION: A via hole(103) is formed in a substrate(102). The substrate is dipped in a first solution(30) so that the via hole is filled with the first solution. A second solution(32) with a metal particle is provided to the first solution so that the metal particle is sunken in the via hole. The substrate with the via hole is processed by heat. A via is formed in the via hole.</p>
申请公布号 KR20110046141(A) 申请公布日期 2011.05.04
申请号 KR20090102999 申请日期 2009.10.28
申请人 发明人
分类号 H01L21/288;H01L21/60;H01L23/12;H01L23/48 主分类号 H01L21/288
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