| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an alignment system of stream data. <P>SOLUTION: The system has: a demultiplexing component for bifurcating the data stream of a double data rate (DDR) into first and second single data rate (SDR) data streams; a delay architecture composed for generating a delayed SDR data stream from the SDR data stream; a logic circuit composed for inspecting the SDR data stream and the delayed SDR data stream, detecting a predetermined bit pattern transmitted by the DDR data stream, and indicating the detection of the predetermined bit pattern; and a data aligning component for determining the number of intervening bits between occurrences of the predetermined bit pattern to produce aligned data with the interposed bit as a frame. <P>COPYRIGHT: (C)2010,JPO&INPIT |
