| 摘要 |
<p>A CMOS-type 6T-SRAM device is composed of vertical transistors (SGT), and in the device, a small SRAM cell area and a stable operation margin are achieved. In a static-type memory cell configured by using six MOS transistors, the MOS transistors configuring the memory cell are formed on a planar silicon layer formed on an embedded oxide film, and a drain, a gate and a source are arranged in the vertical direction. The gate has a structure which surrounds a columnar semiconductor layer, the planar silicon layer is composed of a first conductivity type first active region and a second conductivity type second active region, and the regions areconnected to each other through a silicide layer formed on a surface of the planar silicon layer to form the SRAM cell having a small area.</p> |
