| 摘要 |
A memory architecture includes a matrix of memory cells structured into rows and columns and associated with a row decoder, an array of reference cells associated with the matrix, a first detector block including plural sense amplifiers associated with the matrix in correspondence with its columns, and a plurality of latch registers connected to the output of the sense amplifiers and interconnected to each other by a references bus which further connects them to a second detector block that includes at least one sense amplifier of the reference cells. The array of reference cells is placed upstream of the wordlines of the matrix taking, as reference, a propagation direction of a voltage signal applied to the memory cells. Moreover, the second detector block includes a stabilized buffer suitable to supply the references bus with an output signal having rise transient stable with respect to working conditions of the architecture.
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