发明名称 |
Dual damascene process flow for porous low-k materials |
摘要 |
A method of forming a dual damascene opening comprising the following steps. A structure having an overlying exposed conductive layer formed thereover is provided. A dielectric layer is formed over the exposed conductive layer. An anti-reflective coating layer is formed over the dielectric layer. The anti-reflective layer and the dielectric layer are etched using a via opening process to form an initial via exposing a portion of the conductive layer. A protective film portion is formed over at least the exposed portion of the conductive layer. The anti-reflective coating layer and the dielectric layer are patterned to reduce the initial via to a reduced via and to form a trench opening substantially centered over the reduced via. The trench opening and the reduced via comprising the dual damascene opening.
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申请公布号 |
US7538025(B2) |
申请公布日期 |
2009.05.26 |
申请号 |
US20030714304 |
申请日期 |
2003.11.14 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
CHEN CHAO-CHENG;YEH CHEN-NAN;FU CHIEN-CHUNG |
分类号 |
H01L21/4763;H01L21/316;H01L21/768 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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