发明名称 |
METHOD AND STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS |
摘要 |
A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate. |
申请公布号 |
KR20080028915(A) |
申请公布日期 |
2008.04.02 |
申请号 |
KR20087000524 |
申请日期 |
2006.04.07 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CABRAL CYRIL JR.;GORDON MICHAEL S.;RODBELL KENNETH P. |
分类号 |
H01L21/28;H01L21/3205;H01L23/48 |
主分类号 |
H01L21/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|