发明名称 Semiconductor integrated circuit designing method and program
摘要 An object of the present invention is to prevent occurrence of an unconnected terminal during arrangement and connection, shorten the time required for automatic arrangement and connection, improve a yield, and improve the properties of a cell. A recognized object-of-wiring thinning cell (minimum-rule cell) is temporarily replaced with a preferred-rule cell. Since a block has a free region devoid of a cell, an event that a replaced preferred-rule cell interferes with an adjoining one and is not separated from the adjoining one by a predetermined pitch will not take place. Even when the replaced cell interferes with the adjoining one, since the block has the free region devoid of a cell, the cell can be moved to a position at which it will not interfere with the adjoining one. An event that the cell is not separated from the adjoining one by the predetermined pitch will not take place. When all object-of-wiring thinning cells have been treated, reconnection is performed. When processing is terminated, a region of the block is modified.
申请公布号 US7315995(B2) 申请公布日期 2008.01.01
申请号 US20050072493 申请日期 2005.03.07
申请人 FUJITSU LIMITED 发明人 NISHIWAKI AKIFUMI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址