发明名称 |
Variable delay clock circuit and method thereof |
摘要 |
An apparatus for generating an output clock is disclosed. The apparatus comprises: N variable offset clock circuits for receiving N input clocks and for generating N intermediate clocks having N phase offsets controlled by N intermediate signals, respectively, where N>1; a clock multiplexer for selecting one of the N intermediate clocks as the output clock according to a finite-state signal having N possible states; and a finite-state-machine for receiving a control signal and the N intermediate clocks and for generating the finite-state signal and the N intermediate signals.
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申请公布号 |
US2007247202(A1) |
申请公布日期 |
2007.10.25 |
申请号 |
US20060517415 |
申请日期 |
2006.09.08 |
申请人 |
LIN CHIA-LIANG;CHOU GERCHIH |
发明人 |
LIN CHIA-LIANG;CHOU GERCHIH |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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