| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a circuit which outputs a binarized signal to be inverted in a timing when an analog signal exceeds a threshold value Vref, without chattering even if a high frequency component is superimposed, when binarizing the analog signal. <P>SOLUTION: The binarization circuit comprises: a first comparator circuit 10 in which a signal is inverted when an analog signal Vi is below the threshold value Vref and when it exceeds a higher-side offset threshold value Vref1 set higher than Vref; a second comparator circuit 20 in which a signal is inverted when the analog signal Vi exceeds the threshold value Vref and when it is below a lower-side offset threshold value Vref set lower than the threshold value Vref; and a selection circuit 30 in which output signals of the first comparator circuit 10 and the second comparator circuit 20 are inputted, the inversion phenomenon in the first comparator circuit 10 that occurs when the analog signal value Vi is below the threshold value Vref, and the inversion phenomenon in the second comparator circuit 20 that occurs when the analog signal value Vi exceeds the threshold value Vref, are selected and the outputs are inverted. <P>COPYRIGHT: (C)2008,JPO&INPIT |
