A METHOD FOR PROVING LOGIC CIRCUITS AND THE DEVICE USING THE METHOD

摘要

A method and a device for proving a logic circuit are provided to reduce time required for proving the logic circuit, apply to designing a circuit such as a logic gate or transistor level. The device proves design error of the logic circuit by comparing waveform property of a node in the designed logic circuit with abnormality of the node of the logic circuit to be designed. A function, the timing, and analog signal property of the logic circuit are proved by using waveform information of the node in the logic circuit to be proved.