发明名称 Duty cycle rejecting 2:1 serializing mux for output data drivers
摘要 A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second clocking signal, respectively, to reduce jitter from dependence on the falling edges of the clocking signals. The second clocking signal is 180 degrees out of phase with the first clocking signal to sample the first input data stream in the first unit interval of an output data stream and the second input data stream in the second unit interval of the output data stream. Consequently, a serialized output data stream is driven at twice the frequency of both the first and the second input data streams, including logical information from the first and second input data streams every period of the output data stream.
申请公布号 US2007157048(A1) 申请公布日期 2007.07.05
申请号 US20050322681 申请日期 2005.12.30
申请人 INTEL CORPORATION 发明人 LEVIN ALEXANDER;BADRINARAYANAN SRIRAM;MATTHEWS CHRIS D.
分类号 G06F1/12;G06F13/42 主分类号 G06F1/12
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