发明名称 Display controller capable of reducing cache memory and the frame adjusting method thereof
摘要 A display controller capable of reducing cache memory and a frame adjusting method thereof are provided. The display controller comprises a memory controller, a first memory, a second memory and a frame control circuit. The memory controller is for reading part of the image data from a source layer to obtain a first image data, and reading part of the image data from the target layer to obtain a second image data. The first memory is for storing the first image data. The second memory is for storing the second image data. The frame control circuit is for processing the first image data to generate a first processed image data overlaid with the second image data to obtain a second processed image data. If the second processed image data needs further processing, then the display controller loads the second processed image data to an external memory.
申请公布号 US2007076007(A1) 申请公布日期 2007.04.05
申请号 US20060475157 申请日期 2006.06.27
申请人 QUANTA COMPUTER INC. 发明人 CHEN TE-YI
分类号 G09G5/39 主分类号 G09G5/39
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