Test system and single-chip tester capable of testing a plurality of chips simultaneously

摘要

The present invention relates to a test system, and in particular relates to a test system capable of testing a plurality of chips simultaneously. The test system comprises a single-chip tester and a handler. The single-chip tester further comprises a pattern memory and a micro-processor. The pattern memory comprises a plurality of pattern units for respectively performing a function pattern test on the plurality of chips and generating a test result mapping to the plurality of chips. The micro-processor performs various tests and generating an interface control signal according to the test result. The handler initiates the micro-processor for performing various tests and receives the interface control signal to finish testing the plurality of chips. The pluralities of chips are set to the handler.