发明名称
摘要 PROBLEM TO BE SOLVED: To extremely reduce the generation quantity of jitter as a result by keeping the operation of a voltage-controlled oscillator stable even though spiking noise takes place due to the operation of a phase frequency comparator or a frequency divider in an oscillation circuit using a phase locked loop. SOLUTION: A delay circuit 4 is inserted between an output of the voltage- controlled oscillator 3 and an input of the frequency divider 5, and the delay quantity of the delay circuit 4 is adjusted so that the leading edge and the trailing edge of a clock signal S6 to be returned to the phase frequency comparator 1 from the frequency divider 5 can be separated the most dissociation from the leading and trailing edges of all clock signals existing inside the voltage- controlled oscillator 3.
申请公布号 JP3772668(B2) 申请公布日期 2006.05.10
申请号 JP20000361557 申请日期 2000.11.28
申请人 发明人
分类号 H03K3/353;H03L7/08;H03L7/081 主分类号 H03K3/353
代理机构 代理人
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