| 摘要 |
A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the IC design that do not meet metal density requirements are then identified. The identified one or more regions are then filled with one or more filler metal polygons as a function of the metal density requirement and coupling capacitance between metal lines.
|
