| 摘要 |
A cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices, in particular cached dynamic random access memory (DRAM) and cached static random access memory (SRAM), wherein the data in the cache is written back from cache to the main memory arrays (write-back operation) when power-down is entered such that the cache, tag and much of the cache control logic can be powered-down during power-down standby mode. If a DRAM cache is used, the refresh cycles can be inhibited to the DRAM cache, since it has been powered-down, so that additional power savings can be realized during self-refresh power-down standby. When power-down standby is exited, the cache operations are enabled as soon as the cache, tag and control circuitry are powered-up and a clear tag sequence is executed.
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