发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit wherein a charge pump receives a noise comprising a high frequency component and converts the noise into a noise with a frequency component lower than a cut-off frequency of a loop filter so that it is prevented that the loop filter cannot eliminate the noise, resulting in causing a phase noise to an FSK modulation signal. <P>SOLUTION: The PLL circuit includes: a phase comparator 13 for detecting a phase difference between a reference frequency signal fr and a comparison frequency signal fp and providing an output of a phase comparison signal PD; a low pass filter 31 for eliminating the noise comprising a high frequency component included in the phase comparison signal PD; the charge pump 14 for increasing / decreasing a control current IC in response to the phase comparison signal PD to provide an output; the loop filter 15 for eliminating the high frequency component of the control current IC, converting the control current IC into a control voltage VC and providing an output; and a voltage-controlled oscillator 1 for increasing / decreasing the comparison frequency signal fp in response to the control voltage VC and providing an output. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005347817(A) 申请公布日期 2005.12.15
申请号 JP20040161748 申请日期 2004.05.31
申请人 SHARP CORP 发明人 SHIMODA MAMORU
分类号 H03L7/093;H03L7/18 主分类号 H03L7/093
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