| 摘要 |
PROBLEM TO BE SOLVED: To provide an automatic high-order synthesis method which restrains a decrease in degree of flexibility due to the integration of variable array in a high-order synthesis and generates the RTL description of a logic circuit which is small in circuit area and operates at a high-speed, and a high-order synthesis program therefor. SOLUTION: The automatic high-order synthesis method includes the following steps: a step which reads synthesis-restrictive conditions to be stored in a synthesis restriction storage area, and extracts, from an operational description of a high-order synthesis object, a control data flow graph in which an order of execution of multiple computations is set, the computations being described in the operational description of the high-order synthesis object, based on the synthesis-restrictive conditions; a step which sets order of priority for setting the order of execution of the multiple computations based on the control data flow graph; and a step which allocates variable arrays obtained by the integration of a plurality of variable arrays described in the operational description to a storage device based on the order of priority and performs execution scheduling for setting order for executing the multiple computations. COPYRIGHT: (C)2006,JPO&NCIPI
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