Shift register for configuring bits used to program logic circuits, includes master- and slave latches with analysis logic to output configuration bits

摘要

The master latch (8) provides intermediate storage for a data bit (3) at a serial input (2) of the shift register cell (1). A first slave latch (10) provides intermediate storage for the data bit at the master latch. Analysis logic (13) outputs the configuration bit (6) in accordance with the data bits under intermediate storage in the master- and slave latches.