发明名称 METHOD FOR FORMING METAL INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE TO CONTROL PATTERN DEFECT CAUSED BY THICKNESS DIFFERENCE OF PHOTORESIST GENERATED BY DENSITY DIFFERENCE OF VIA HOLE
摘要 PURPOSE: A method for forming a metal interconnection layer is provided to control a pattern defect caused by a thickness difference of photoresist by forming a partial via hole while forming a photoresist layer or a buried material layer in the via hole. CONSTITUTION: The first stopper layer is formed on a semiconductor substrate(400) having the first conductive layer(402). An interlayer dielectric is formed on the first stopper layer(404). A hard mask layer functioning as an ARC(anti-reflective costing) is formed on the interlayer dielectric. The first photoresist pattern is formed on the hard mask layer to define a via hole(412) connected to the first conductive layer. The hard mask layer and the interlayer dielectric are partially etched to form a partial via hole. The remaining first photoresist pattern is removed. A photoresist layer is formed. The photoresist layer is left in the partial via hole while the second photoresist pattern for defining a trench interconnection region that at least partially overlaps the partial via hole is formed. The hard mask layer is etched to form a hard mask layer pattern. The remaining second photoresist pattern is removed. The interlayer dielectric is partially etched to form the trench interconnection region and a full via hole to which the partial via hole is extended. The first stopper layer exposed to the lower part of the full via hole is eliminated. The full via hole and the trench interconnection region are filled with the second conductive layer.
申请公布号 KR20050007004(A) 申请公布日期 2005.01.17
申请号 KR20030047006 申请日期 2003.07.10
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 HAH, SANG ROK;KIM, IL GOO;LEE, KYOUNG WOO;SON, SA EIL
分类号 H01L21/3065;H01L21/3205;H01L21/768;(IPC1-7):H01L21/320 主分类号 H01L21/3065
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