Flash memory comprising means for controlling and refreshing memory cells in the erased state

摘要

The method involves applying a positive erasing voltage (VERpos) on a control gate (G) of a floating gate transistor. A positive erasing voltage (VD) is applied to a drain (D) of the floating gate transistor by a programming lock. The positive error voltage (VD) is equal to a programming voltage (Vprog2) provided by the lock at the time of programming of the transistor. An independent claim is also included for a flash memory.