| 摘要 |
A register-controlled delay locked loop (RDLL) circuit for area reduction, includes a first clock buffer for generating a falling clock signal, which is activated at a rising edge of an inverted external clock signal, a second clock buffer for generating a rising clock signal, which is activated at a rising edge of an external clock signal, a clock multiplexer for outputting a single clock signal made by combining the falling clock signal and the rising clock signal, a delay line for delaying the single clock signal to generate a delayed single clock signal, and a controller for controlling the delay line so as to adjust amount of delay of the single clock signal.
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