| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit that avoids a problem of deviation between the center of a phase detection characteristic of a phase detector and the center of a frequency detection window of a frequency detector caused by the provision of a delay circuit for delaying a reference clock by eliminating the need for the delay circuit as above and can match the center of the phase detection characteristic of the phase detector with the center of the frequency detection window of the frequency detector independently of the frequency of the reference clock. <P>SOLUTION: A T flip-flop 37 generates a clock CLK_A0 resulting from the application of 1/2 frequency division to a clock CLK_B outputted from a voltage-controlled oscillator 21 and a clock CLK_A90 whose phase is led by 90 degrees with respect to the phase of the clock CLK_A0, supplies the clock CLK_A0 to the frequency detector 30, and supplies the clock CLK_A90 to an EXOR circuit 29 acting like the phase detector. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
