| 摘要 |
<P>PROBLEM TO BE SOLVED: To adjust a clock deviation between a transmitting side system and a receiving side system. <P>SOLUTION: When the amount X of received data stored in a buffer 10 is larger than a reference value B and smaller than a reference value A, a selector 40 gives a reference clock CK0 from a frequency dividing circuit 32 as a clock CK to a D/A converter 50. When the amount X of the received data is equal to and larger than the reference value A, the selector 40 alternately gives the reference clock CK0 and a high-speed clock CK1 for a prescribed period each as a clock CK to the D/A converter 50. When the amount X of the received data is not larger than the reference value B, the select or 40 alternately gives the reference clock CK0 and a low-speed clock CK2 for a prescribed period each as a clock CK to the D/A converter 50. The D/A converter 50 obtains the received data from the buffer 10 and converts the received data into an analog signal. <P>COPYRIGHT: (C)2004,JPO |
