发明名称 SEMICONDUCTOR MEMORY CIRCUIT, IN WHICH A BURN-IN TEST IS REALIZED
摘要 PURPOSE: A semiconductor memory circuit is provided to perform a burn-in test by giving a high potential difference between bit line pair even when using a thin film transistor in a sense amplifier. CONSTITUTION: The semiconductor memory circuit has a normal operation mode and a burn-in test mode, and comprises a memory cell array(1) having a plurality of memory cells(MC) arranged in a matrix. Pairs of bit lines(BL1,/BL1,BL2,/BL2) are prepared in a row of the memory cell array, and a plurality of word lines(WL) are prepared in a column of the memory cell array. The memory cells are located at a cross point of the bit line and the word line, and comprises one transistor and one condenser.
申请公布号 KR20040042796(A) 申请公布日期 2004.05.20
申请号 KR20030056309 申请日期 2003.08.14
申请人 RENESAS TECHNOLOGY CORP. 发明人 TSUKIKAWA YASUHIKO
分类号 G01R31/30;G01R31/28;G11C7/12;G11C7/18;G11C11/401;G11C29/06;G11C29/12;(IPC1-7):G11C11/401 主分类号 G01R31/30
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