发明名称 SLEW RATE CONTROL SYSTEM OF OUTPUT DATA
摘要 PROBLEM TO BE SOLVED: To control the slew rate of output data and to improve an output data window when a potential difference between an output power source and an inner power source changes. SOLUTION: The slew rate control system of output data is provided with a VDD-VDDQ potential difference detection circuit 1 detecting reduction of the potential difference between the first power source VDD and the second power source VDDQ, generating a first signal SLP at prescribed timing, detecting the increase of the potential difference between the first power source and the second power source, and generating a second signal SLN, and a slew rate control circuit 2 which controls transition speed in falling of output data to be large when the first signal SLP is significant, which controls transition speed in rising of output data to be large when the second signal SLN is significant and generates output data. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004135098(A) 申请公布日期 2004.04.30
申请号 JP20020298009 申请日期 2002.10.10
申请人 ELPIDA MEMORY INC 发明人 SHIBATA TOMOYUKI;OOISHI TSURATOKI
分类号 H03K5/12;G11C11/409;H03K17/687;H03K19/003;H03K19/0175;(IPC1-7):H03K5/12;H03K19/017 主分类号 H03K5/12
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