发明名称 Instruction execution apparatus
摘要 An instruction execution apparatus comprising a register 43 for storing a copy of contents of the maximum number of entries that are executable simultaneously in one cycle with the entry storing the oldest unreleased instruction at the head among all entries in an instruction storage device 42 after execution of the instructions, a completion condition determination section 44 for determining whether the instructions stored in the entries of the register are completed in the cycle for determining completion conditions of the entries in the instruction storage device, and an entry release section 45 for releasing only the entries that are determined to be completed by the completion condition determination section among all entries in the instruction storage device, which allows the entries in the CSE to be released smoothly even though the number of entries in the CSE, or clock frequency, is increased.
申请公布号 US2004006684(A1) 申请公布日期 2004.01.08
申请号 US20020331917 申请日期 2002.12.31
申请人 FUJITSU LIMITED 发明人 AKIZUKI YASUNOBU;INOUE AIICHIRO
分类号 G06F9/38;G06F9/30;(IPC1-7):G06F9/30 主分类号 G06F9/38
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