发明名称 System and method for implementing a counter
摘要 A counter is provided which can be implemented in flash memory allowing longer life through fewer erasures. The counter is incremented using a method that minimizes bit transitions from 1 to 0. In one embodiment, the counter is implemented in m+n bits. The bits of the counter are grouped into a binary portion of the counter of m bits and a unary portion of the counter of n bits. In order to increment the counter, the unary portion of the counter is incremented first. When the unary portion of the counter reaches a specific value, the binary portion of the counter is incremented. This limits 1 to 0 bit transitions and allows a large range of unique values to be read from the counter. In another embodiment, two unary counters are formed, which dynamically change in size as the counter is incremented.
申请公布号 US2004003189(A1) 申请公布日期 2004.01.01
申请号 US20020185055 申请日期 2002.06.28
申请人 ENGLAND PAUL;PEINADO MARCUS 发明人 ENGLAND PAUL;PEINADO MARCUS
分类号 G06F12/16;G11C16/10;G11C16/34;H03K21/00;H03K21/40;(IPC1-7):G06F12/00 主分类号 G06F12/16
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