| 摘要 |
1,157,851. Charging and discharging capacitors. HUGHES AIRCRAFT CO. 3 Jan., 1967 [21 Jan., 1966], No. 308/67. Heading H2H. A pulse welding apparatus in which a capacitor is charged through a first switch and discharged through a second switch has first, second and third timing circuits MV1-MV3 each generating a timing pulse, arranged so that the switches are controlled in a predetermined sequence, the pulses being of diminishing duration. The second timing circuit maintains the first switch conductive for almost all of a duration of the second timing pulse, and the third timing circuit causes the second switch to become conductive after termination of the third timing pulse which is sufficient to allow the second timing pulse to render the first switch non-conductive thereby preventing simultaneous conduction of the first and second switches, and the first timing circuit, which is connected to the second and third timing circuits prevents re-initiation of the operating cycle prior to the re-charging of the capacitor. A storage capacitor 16 is connected to a supply through a thyristor SCR1 and to a welding transformer 72 through another thyristor SCR2, the thyristors being rendered conductive alternately but not simultaneously. On closure of a switch 22 a capacitor C1 previously charged through resistors R1, R5, discharges through resistor R5 rendering a transistor Q1, forming part of a monostable flip-flop, non-conductive and Q2 conductive which discharges a previously charged capacitor C2 through resistors R3, R4, and at a given point in the discharge the flip-flop returns to its original state. Also when Q2 is rendered conductive, a second flip-flop MV2 is switched causing the base drive of another transistor Q3 and hence the gate voltage of SCB1 to drop to zero hence SCR1 ceases to conduct at the next half-cycle zero for the period of MV2. A third flip-flop MV3 is switched from MV2 causing a capacitor C5 to discharge through a diode CR2. At the end of the period of MV3 its output voltage goes positive causing the collector of transistor Q4 to become more positive and the base of Q5 to become less positive until its emitter triggers thus discharging a capacitor C7 to the primary winding of a transformer T1 thus triggering SCR2 and discharging capacitor 16. The delay time of MV3 is arranged so that SCR1 will not fire until SCR2 has opened. The delay time of MV2 is arranged to effect this. |
