发明名称
摘要 PROBLEM TO BE SOLVED: To generate a plurality of serial signals whose periods and whose duty ratio differ without the use of timer coincidence interrupt processing. SOLUTION: A processing circuit 31 of a side face controller 7 selects a serial bit signal in combination with a plurality of unit signals and interval signals alternately corresponding to a shock signal based on an output of a shock sensor 4. A designation circuit 32 reads each unit signal of a selected serial bit signal one by one signal each from memories 33, 34 and transfers the read signal as a parallel bit signal to a shift register 36. For this transfer period, the processing circuit 31 allows the shift register 36 to introduce a 2nd signal of a level corresponding to a final bit of the preceding unit signal to a conductor wire 38. After the transfer of the unit signal, the processing circuit 31 allows the shift register 36 to introduce bits of the unit signal sequentially one by one bit each in series synchronously with a clock signal. The shock signal is generated on the conductor wire 38 by repeating the operation above.
申请公布号 JP3352343(B2) 申请公布日期 2002.12.03
申请号 JP19960312305 申请日期 1996.11.22
申请人 发明人
分类号 G08C19/28;B60R21/01;B60R21/16;H03K3/78;H03K5/13;H03K5/131 主分类号 G08C19/28
代理机构 代理人
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