| 摘要 |
PURPOSE: An improved push-pull cascode logic circuit is provided to improve an operating speed thereof by setting a threshold voltage of NMOS transistors of a binary tree section lower than that of NMOS transistors of a cross-couple latch. CONSTITUTION: A cross-couple latch(100) is connected to a supply voltage. The cross-couple latch(100) includes PMOS transistors(MP10,MP12) and NMOS transistors(MN10,MN12). A binary tree section(200) is connected to the supply voltage, a ground voltage, and output terminals(N1,N2) of the cross-couple latch(100). The binary tree section(200) includes a plurality of NMOS transistors(MN14-MN24). Each of the NMOS transistors(MN14-MN24) has a threshold voltage lower than that of each of the PMOS transistors(MP10,MP12) and NMOS transistors(MN10,MN12) of the cross-couple latch(100).
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