发明名称 VARIABLE DELAY CIRCUIT, ITS SETTING METHOD AND SEMICONDUCTOR TEST DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To avoid the effect caused by the sink phenomenon in the case of measuring the delay time of a variable delay circuit. SOLUTION: A circuit adopting the setting method of this invention is provided with a memory that stores the correlation between the combination of delay sections causing a delay time among delay sections 1a-1n and the delay time and is further provided with an offset section 10 that is connected in series with the delay sections and produces a delay time to shift the period of self- running loop oscillation to a period other than that in the vicinity of a multiple period when the period of the self-running loop oscillation is close to the multiple period of the operating period of surrounding electric circuits in the case of measuring the delay time by the combination of the delay sections in the self-running loop oscillation state in order to set the correlation to this memory.</p>
申请公布号 JP2002076860(A) 申请公布日期 2002.03.15
申请号 JP20000264025 申请日期 2000.08.31
申请人 ADVANTEST CORP 发明人 OCHIAI KATSUMI
分类号 G01R31/28;G01R31/319;H03K5/14;(IPC1-7):H03K5/14 主分类号 G01R31/28
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