| 摘要 |
The present invention relates to improved adaptive filtering techniques and architectures. Preferably, this filtering is performed as part of the digital processing that occurs with a digital signal processor. It is a feature of this invention that the adaptive filtering taught herein provides the advantages of both serial and parallel architectures, without the accompanying disadvantages thereof. In particular, an adaptive filter is taught that possesses low pin counts, fast processing times suitable for high-speed applications and reduced numbers of filter elements. In a preferred embodiment, the inputs and outputs of the adaptive filter are supplied to and from the adaptive filter in a serial manner while the processing is performed internally within the adaptive filter in a parallel manner. The parallel processing is preferably effected by a delayed least-means-squares algorithm implemented using a single adder, a single multiplier and a single multiplier-accumulator instead of by numerous such adders, multipliers and multiplier-accumulators.
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