发明名称 DLL CIRCUIT WITH MASTER-SLAVE STRUCTURE
摘要 PURPOSE: A DLL(Delay Locked Loop) circuit with a master-slave structure is provided to generate an internal clock by using a received external clock. CONSTITUTION: A phase comparator(322) of a master DLL(32) generates a detection signal(DS) by comparing an external clock(ECLK) with a phase of a feedback signal(FD). A delay control portion(324) receives the detection signal(DS) and generates the first delay control signal(DCON1). The first digital delay portion(326) delays the external clock as much as a delay time according to the first delay control signal(DCON1). A compensating delay portion(328) delays an output signal of the first digital delay portion(326) as much as a compensating time and generates the feedback signal. A digital filter(342) removes a high frequency component from the first delay control signal(DCON1) and generates the second delay control signal(DCON2). The second digital delay portion(344) delays the external clock(ECLK) as much as the external clock(ECLK) according to the second delay control signal(DCON2). and generates an internal clock(ICLK).
申请公布号 KR20010091534(A) 申请公布日期 2001.10.23
申请号 KR20000013348 申请日期 2000.03.16
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, GYU HYEON
分类号 H03L7/187;H03L7/081;(IPC1-7):H03L7/187 主分类号 H03L7/187
代理机构 代理人
主权项
地址