发明名称 |
Methods and circuits for correcting a duty-cycle of a signal by delaying the signal and generating an output signal responsive to state transitions of the signal and the delayed version of the signal |
摘要 |
A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.
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申请公布号 |
US2001030562(A1) |
申请公布日期 |
2001.10.18 |
申请号 |
US20010826566 |
申请日期 |
2001.04.05 |
申请人 |
KIM KYU-HYOUN;LEE JUNG-BAE |
发明人 |
KIM KYU-HYOUN;LEE JUNG-BAE |
分类号 |
H03K5/04;H03K5/13;H03K5/156;H03L7/081;(IPC1-7):H03K3/017 |
主分类号 |
H03K5/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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