| 摘要 |
Methods for testing semiconductor memory devices are performed during the writing and reading of test information to and from memory cells. During the tests, operational parameters such as commencement of timing signals and the voltage levels thereof which are employed to activate components of a memory device are controllably adjusted in an effort to intentionally imbalance or alter the voltage differential appearing on the bit lines. If the memory device has a defect, the voltage levels on the bit lines are altered to such a degree that the sense amplifier, although properly sensing the voltage differential, incorrectly senses the intended test information stored in the memory cells. As the parameters are manipulated, the test information written from the memory cell and error signals are generated when the information is not the same. Circuitry for performing methods for testing semiconductor memory devices during the writing and reading of test information to and from memory cells is also disclosed. Such circuitry includes signal generation circuitry for generating timing signals, preparatory and control circuitry for preparing and selecting individual memory cells, word lines and bit lines for read and write operations, and analyzing circuitry to evaluate the results of the sense amplifier and the data written into and read from the memory cells and to discern defects in the memory cells.
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