Ferroelektrischer Transistor und dessen Verwendung in einer Speicherzellenanordnung

摘要

According to the invention, a first source-drain region (121), a channel region (13) and a second source-drain region (122) are located in a semiconductor substrate (11). A dielectric layer (14) covers at least the surface of the channel region and parts of the first source-drain region. On the surface of said dielectric layer, a ferroelectric layer (17) is provided between two polarization electrodes (16, 18). A gate electrode is positioned on the surface of the dielectric layer. The thickness of the dielectric layer is measured in such a way that a remanent polarization of the ferroelectric layer which is aligned between the two polarization electrodes, generates compensation charges in one section of the channel region. The ferroelectric transistor is suitable for use a memory cell in a memory cell arrangement.