发明名称 SIGNAL PROCESSOR
摘要 A 32-bit data bus (18) is used to transfer data between a memory control block (15), an error correction block (16) and a host I/F block (17), while a 64-bit memory data bus (19) is used to transfer data between a buffer memory (12) and the memory control block (15). The buffer memory (12) is accessed for 64 bits at a time, and each of the blocks process 32 bits at a time. As a result, 32-bit data transmitted on the data bus (18) between blocks are always effective, and the access speed from each block in the system to the buffer memory (12) increases.
申请公布号 WO0118639(A1) 申请公布日期 2001.03.15
申请号 WO1999JP04863 申请日期 1999.09.08
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.;AOKI, TORU 发明人 AOKI, TORU
分类号 G06F3/06;G06F11/10;(IPC1-7):G06F3/06;G11B20/18;G06F12/16 主分类号 G06F3/06
代理机构 代理人
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