| 摘要 |
PROBLEM TO BE SOLVED: To actually reduce a cache error penalty in a fetch access to an interrupt handler at the occurrence of interrupt in an information processing system having a cache memory. SOLUTION: This cache memory is provided with an address holding part 5 optionally holding an address, and also, an optional address value held by the part 5 can be compared with tag memory data in the cache memory. When interrupt takes place, cache hit error decision is previously performed by an address value held by the part 5 apart from a cache access request from a CPU 20. It is possible to previously discriminate whether the address of an interrupt handier is subject to a cache hit or an error before the CPU 20 accesses the interrupt handler by setting the address of the interrupt handler in the part 5.
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