| 摘要 |
A clock frequency multiplying apparatus is disclosed. The apparatus includes a clock generator for generating a clock signal, a data input buffer for serially receiving a data, address, instruction, etc. when a transmission clock signal generated by the clock generator is inputted, a data shift register for grouping the data received through the data input buffer into a data packet and, in parallel, transferring the same to a memory, and a clock frequency multiplier for multiplying a transmission clock frequency generated by the clock generator and inputting the same into the data shift register for implementing a fast data transfer by multiplying a clock frequency by dividing the clock signal in an internal circuit of the DRAM into a critical path and a non-critical path by using a transmission clock signal for the critical path and the multiplied clock signal for the non-critical path and enhancing an internal data transfer ratio.
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