发明名称 |
CLOCK NON-HIT SWITCHING DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To obtain a clock non-hit switching device that can realize a non-hit switching, only by providing a circuit simpler than a PLL in each slave unit. SOLUTION: A clock synchronization unit 100a and a clock synchronization unit 100b output clock CLK2, CLK4 that are highly phase-locked to a slave unit 200. A selector 12C selects a clock fed to a function section 16 which is under the control of a switching control section 15. The switching control section 15 controls the selector 12C, so that switching is conducted for a period when the clocks CLD2, CLK4 are both at L or H level. |
申请公布号 |
JP2000269945(A) |
申请公布日期 |
2000.09.29 |
申请号 |
JP19990068601 |
申请日期 |
1999.03.15 |
申请人 |
HITACHI TELECOM TECHNOL LTD |
发明人 |
ONODERA MASAHIRO;OTA YUKINORI |
分类号 |
H03K5/00;G06F1/04;H03K17/00;H03L7/00;H04B1/74;H04L1/22;H04L7/00 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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