发明名称 |
Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices |
摘要 |
The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to the primary bus and the secondary bus. Additionally, a second secondary processor is connected to the secondary bus. The first secondary processor and the second secondary processor forms cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.
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申请公布号 |
US6065085(A) |
申请公布日期 |
2000.05.16 |
申请号 |
US19980013818 |
申请日期 |
1998.01.27 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
ODENWALD, JR., LOUIS H.;SCHREMMER, STEVEN R. |
分类号 |
G06F13/40;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/40 |
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