发明名称 |
SEMICONDUCTOR MEMORY CIRCUIT |
摘要 |
PURPOSE: A semiconductor memory circuit is provided to be capable of reducing a chip size without lowering a redundancy efficiency. CONSTITUTION: A plurality of memory cell array(240) are disposed in rows and columns. A decoder circuit(250) selects a predetermined memory cell array of the plurality of memory cell arrays. A sense amplifier(260) senses data from the selected memory cell array. The plurality of memory cell arrays is composed of a first type of memory cell arrays having redundant memory cells and a second type of memory cell arrays not having redundant memory cells. A select circuit selects the selected memory cell array or the redundant memory cell array.
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申请公布号 |
KR20000022818(A) |
申请公布日期 |
2000.04.25 |
申请号 |
KR19990036539 |
申请日期 |
1999.08.31 |
申请人 |
FUJITSU LIMITIED |
发明人 |
AIKAWA TADAO;SZUKI TAKAAKI;SATO YASHARU;KOBAYASHI HIROYUKI |
分类号 |
G11C11/407;G11C7/00;G11C11/401;G11C29/00;G11C29/04;H01L21/8242;H01L27/108;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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